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[VHDL-FPGA-Verilog] 15AlteraDEIP

Description: 15个Altera的IP的源码.15个Altera的IP的源码-15 Altera s IP source .15 months of Altera s IP source
Platform: | Size: 49152 | Author: 11 | Hits:

[SCM] 8051ipcore

Description: 8051的IP内核，用verilog编写，可以实现8051的一般功能-8051 IP core, prepared using Verilog, you can realize the general function of 8051
Platform: | Size: 52224 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] 8255

Description: Verilog语言描述的Intel8255 IP Core，本人已经在某项目中经过了物理验证的，可直接用于FPGA综合或ASIC综合。
Platform: | Size: 6144 | Author: David.Mr.Liu | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] camera.tar

Description: 摄像头的硬件函数，ip核，用于xilinx公司的virtex4 fpga-Camera
Platform: | Size: 416768 | Author: 惠普 | Hits:

[VHDL-FPGA-Verilog] bluetooth

Description: ip核，蓝牙bluetooth的fpga硬件实现-ip nuclear, Bluetooth bluetooth realize the FPGA hardware
Platform: | Size: 16384 | Author: 惠普 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA
Platform: | Size: 23552 | Author: 王鹏 | Hits:

[MPI] I2C

Description: I2C总线的verilog 程序，非常有用，已经经过验证。-Verilog I2C bus procedures, very useful, has been verified.
Platform: | Size: 70656 | Author: LLT | Hits:

[VHDL-FPGA-Verilog] SRAM_16Bit_512K

Description: Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
Platform: | Size: 11264 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] ISP1362

Description: Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform: | Size: 18432 | Author: zhyy | Hits:

[Software Engineering] ps2_ipcore_design

Description: 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计 王 豪黄启俊常 胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的 设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
Platform: | Size: 126976 | Author: Morgan | Hits:

[Algorithm] xapp371

Description: xilinx里的乘法器ip核程序，booth乘法 wallace tree算法 4-2压缩编码 超前进位加法-Xilinx multiplier ip
Platform: | Size: 87040 | Author: 王凯 | Hits:

[OS program] 16cpu

Description: 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
Platform: | Size: 440320 | Author: gimel_sh | Hits:

[Crack Hack] sha_core

Description: 安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box
Platform: | Size: 69632 | Author: 金鑫 | Hits:

[VHDL-FPGA-Verilog] photo_verilog

Description: verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
Platform: | Size: 21504 | Author: sq | Hits:

[SCM] 8051_IP_Verilog

Description: 8051单片机源码verilog版本 包括rtl， testbench， synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
Platform: | Size: 508928 | Author: carol | Hits:

[OS program] 8086IP

Description: 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
Platform: | Size: 71680 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:
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